例句與造句

1. Processor _ architecture : lists the processor ' s chip architecture
   列出了處理器的芯片架構(gòu)。
2. The name of the common chip architecture for ibms pseries and iseries servers
   Ibm的pseries和iseries服務器通用芯片體系結(jié)構(gòu)的名字。
3. Integration of software - based system - on - a - chip architectures with " 4g " networks is anticipated in the next few years
   整合軟體系統(tǒng)晶片結(jié)構(gòu)以4g網(wǎng)路是被期望在什麼時候
4. E : integration of software - based system - on - a - chip architectures with " 4g " networks is anticipated in the next few years
   整合軟體系統(tǒng)晶片結(jié)構(gòu)以4g網(wǎng)路是被期望在什麼時候
5. In this survey we explore the hardware aspects of reconfigurable computing machines , from single chip architecture to multichip systems , including internal structure and external coupling
   在某一時刻一條指令執(zhí)行過程中整個處理器的部件都服務于盡快完成這條指令，至少在概念上如此。
6. It's difficult to find chip architecture in a sentence. 用chip architecture造句挺難的
7. The pssc superchip , a single - chip implementation of the power2 s eight - chip architecture , powered the 32 - node ibm deep blue supercomputer that beat world champion garry kasparov at chess in 1997
   Pssc超級芯片是power2這種8芯片體系結(jié)構(gòu)的一種單片實現(xiàn)，使用這種芯片配置的一個32節(jié)點的ibm深藍超級計算機在1997年擊敗了國際象棋冠軍garry kasparov 。
8. In terms of reliability , another advantage of this approach is that if copies of the sub - job are sent to machines with different architectures , we can protect ourselves against potential errors introduced by a chip architecture , operating system or compiler
   從可靠性來講，這種方法的另外一個優(yōu)點是，如果子任務的不同拷貝被發(fā)送到不同架構(gòu)的機器上，我們就可以避免由于一種芯片架構(gòu)、操作系統(tǒng)或編譯器而引起的潛在錯誤。
9. 10 wallner s . a configurable system - on - chip architecture for embedded devices . in ninth asia - pacific computer systems architecture conference acsac 2004 , beijing , china , springer , lncs 3189 , sept . 7 - 9 , 2004 , pp . 58 - 71 . 11 wallner s . design methodology of a configurable system - on - chip architecture
   它結(jié)合了大量的宏模塊資源，包括一個類標量處理器內(nèi)核粗粒度可配置的處理陣列嵌入式的存儲器，以及由微任務控制器mtc監(jiān)控的定制模塊。
10. At light loads , the architecture allows the chip to “ skip ” cycles to reduce power dissipation . in the circuit design , the basic principle and small signal model of the boost power stage are given at first , and then the stability and small signal model of the control loop are also analyzed , finally , the whole chip architecture and sub - block parameters are presented according to the application requirements
    在電路設(shè)計中,首先闡述了升壓型直流轉(zhuǎn)換器的功率輸出級的拓撲結(jié)構(gòu)、基本原理、小信號模型,然后分析了電流模式控制回路的穩(wěn)定性及小信號模型,最后根據(jù)應用要求進行了電路的總體架構(gòu)設(shè)計,完成了每個子電路的各種參數(shù)的分析、計算。
11. The chip is accomplished in the full cooperation with other team members , the author pays particular attention to the analysis of the whole chip architecture and three sub - block design : transconductance amplifier ( ota ) , voltage reference and current reference . based on existed technologies , a new high order temperature compensated voltage reference and a creative current reference with high order temperature compensation are shown respectively . the author simulated all the sub - block and whole chip by hspice
    該芯片的設(shè)計是由小組成員共同完成,本人主要負責了總體電路的分析、聯(lián)合仿真驗證及以下三個子電路的設(shè)計: 1 、跨導放大器,詳細分析了bandgap跨導放大器輸入級的動靜態(tài)特性及其優(yōu)缺點,并結(jié)合系統(tǒng)要求,設(shè)計了一種與cmos工藝相兼容、可替代bandgap跨導放大器的低壓共源共柵跨導放大器。